1 Introduction This article describes the multi-processor parallel communication system, using the 89C51 as a host, multi-chip 89C2051 as a slave. (89C2051 is a 20-pin 300 MIL package, with 2K FLASH E2PROM MCU, in addition to the lack of two parallel ports, with MCS-51 series MCU all the functions. Because of its small size, strong features, will be widely used in microcontroller applications ). This parallel communication method is suitable for the role of a communication controller in a multi-site, multi-level detection and control system; it is also suitable for use as a microcontroller serial port expansion circuit. Figure 1 The logic diagram of the chip and the four operating states Figure 2 Schematic diagram of single-chip microcomputer parallel communication 2 tri-state bus buffer register 74HC646 In a multi-machine parallel communication system composed of single-chip microcomputers, information exchanges on the bus generally use methods such as PIO (parallel interface) and dual-port registers, and assist in bus arbitration circuits. Commonly used parallel interface chips are 81,8555 and so on. This article describes a simple parallel interface circuit that can replace a chip such as the 8255 chip, as well as make the circuit structure simpler and more compact. The circuit consists of a 74HC74 and a 74HC646 (300MIL narrow package). 3 MCU parallel communication principle 74HC646 latches the data only for the completion of data exchange information preparation, the realization of the communication between the multi-machine microcontroller must also have communication means to enable the microcontroller to understand the working status of the bus to avoid bus collisions. Four-line handshake is used here: two are sent by the sender to the receiver to inform the receiver that the data is ready (eg TFNE*, RFNE* in Figure 2); two are sent by the receiver to the sender, notifying the sender that the data has been Received (TFNF*, RFNF* in Figure 2) communication contact signal is generated by the 74HC74 circuit. SCM parallel communication block diagram shown in Figure 2. 4 multi-machine parallel communication protocol The above parallel communication MCU does not block the circuit to prevent the master and slave from writing to the 74HC646 at the same time or at the same time. Therefore, when the individual units transmit in both directions, they must control their own next operations according to the status information, that is, communicate with each other, through software, Hardware communication protocol coordination can avoid errors and guarantee that the 74HC646 will not cause contention. Therefore, in addition to the above-mentioned contact circuit, the following protocols must also be complied with when preparing the software: 5 Communication protocol format and implementation process 5.1 Information Format <br> In the asynchronous communication transmission of parallel communication, there is also the problem of the frame type and format. A frame format similar to that of serial communication can be used: 5.2 Implementation process of communication protocol <br> The following uses the detection method as an example to illustrate the implementation of the communication protocol. 6 flow chart (detection method) The program flow using the detection method is shown in Figure 3. Fig. 3 Flow chart of the program using detection If you use interrupt mode, you only need to slightly modify the execution process and flowchart. Jiangsu Fast Pack Co., Ltd , https://www.fastmetalpack.com
The 74HC646 is a tri-state bus buffer register. It is actually a dual-port shared memory, but the shared memory area is very small. There is only one data input register and one data output register. Use it as a temporary transfer point for single-byte communication data. One byte is transmitted, the master and slave handshake once, the data is taken away and the next byte of communication continues. The 74HC646 can latch the data of two buses and then exchange data by the internal bus of the chip. The 74HC646 has four operating states. Using these four operating states, multiple microcontrollers can use the data port to exchange data and save the rest of the ports for other tasks such as driving LEDs and controlling switches. The logic diagram of 74HC646 chip and four kinds of working states are shown as in Fig. 1.
When the host sends data to the 74HC646, 74HC646 must ensure that the receiving register is empty.
Data transmission between master and slave through 74HC646, 74HC646 protocol does not allow to operate both simultaneously, you must control their operation according to the status information.
5.2.1 Host Writes to Slave: (Host Write, Slave Read)
The host writes data to the 74HC646, then informs the slave that there is data, and the slave reads the data from the 74HC646.
1 The host reads the status bit and detects if the TFNF* bit is zero.
2 If TFNF*=1, the host temporarily waits; if TFNF*=0, the host writes data to 74HC646 so that TFNF*=1 and TFNE*=0.
3 The slave reads the status bit and detects if the TFNE* bit is zero. If TFNE* = 1, the slave temporarily waits; if TFNE* = 0, the slave reads the data from 74HC646 so that TFNE* = 1 and TFNF* = 0 at the same time.
4 The host computer again detects whether the status bit TFNF* is zero. If it is "0", it indicates that the slave has taken data from the 74HC646 and the host can send the next data.
5.2.2 Host Read Slave Process: (Slave Write, Host Read)
The slave writes data to the 74HC646, and then informs the host that there is data. After the host receives the signal, it removes the data from the 74HC646.
1 The slave reads the status bit and detects if the RFNF* bit is zero.
2 If RFNF*=1, the slave waits for a while; if RFNF*=0, the slave writes data to 74HC646, making RFNF*=1 and making RFNE*=0.
3 The host reads the status bit and detects if the RFNE* bit is zero. If RFNE*=1, the host waits temporarily; if RFNE*=0, the host reads data from 74HC646, makes RFNE*=1, and causes RFNF*=0.
4 The slave detects again if the status bit RFNF* is zero. If it is “0â€, the slave has removed the data from the 74HC646 and the master can send the next data. 